| abstract |
A wafer level package according to an embodiment of the present invention includes a wafer member having a circuit element in a hollow inside thereof, a sealing member provided on an inner surface of the wafer member and provided to enclose an element section having the circuit element, And a gap sealing wall member which is provided on an outer wall surface of the element sealing wall member and hermetically provides a gap section which is a space between the plurality of element sections. |