| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8825 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8413
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-122
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1253
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1233
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8416 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate |
2015-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd9712a7a179e0cc51438f4ea118f470 |
| publicationDate |
2017-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20170048968-A |
| titleOfInvention |
Memory device and method of manufacturing the same |
| abstract |
A plurality of lower word lines extending in a first direction parallel to an upper surface of the substrate on the substrate; A plurality of common bit lines extending in a second direction different from the first direction and parallel to an upper surface of the substrate on the plurality of lower word lines; A plurality of upper word lines extending in the first direction on the plurality of common bit lines; A plurality of first memory cell pillars disposed at a plurality of intersections of the plurality of lower word lines and the plurality of common bit lines and each including a first select element having an ovonic threshold switching characteristic and a first memory layer, ; And a plurality of second memory cells, each of which is disposed at a plurality of intersections of the plurality of upper word lines and the plurality of common bit lines, each including a second selection element having an ovonic threshold switching characteristic and a second memory layer Wherein the plurality of first memory cell pillars and the plurality of second memory cell pillars have a symmetrical structure along a third direction perpendicular to the first direction around the plurality of common bit lines. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20190052889-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20190004163-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109768158-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109216542-A |
| priorityDate |
2015-10-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |