| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-173
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-173 |
| filingDate |
2010-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb761a089dba691e10fe050a316ea73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01586b738d5c3da823a8b306e0b71efa |
| publicationDate |
2017-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20170034935-A |
| titleOfInvention |
Semiconductor device, logic circuit, and cpu |
| abstract |
In order to provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, the nonvolatile latch circuit is configured such that the output of the first element is electrically connected to the input of the second element, A latch having a loop structure electrically connected to an input of the first element; And a data holding unit configured to hold data of the latch unit. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel forming region is used as a switching element. Further, a capacitive element electrically connected to the source electrode or the drain electrode of the transistor is included. |
| priorityDate |
2009-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |