| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13067
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6681 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41725
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28158
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2015-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aafc61a728af8018dcc0538bc21521d4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5cf7d5a7b8f41267d266e4277c60d300
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d694c70b2a2aec4e0465153f5ab6a088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e7fba587c4d8925da25f15a151f79ad
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2ee6eab1accdaa83a3e82a306406ad7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7ed7024cb85e06b04dcd9373bd74a0e |
| publicationDate |
2016-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20160134425-A |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
A semiconductor device includes: a pin structure disposed on a substrate; A gate structure disposed over a portion of the pin structure; A source / drain structure comprising a portion of a fin structure wherein the gate structure is not covered; An interlayer dielectric layer formed over the fin structure, the gate structure and the source / drain structure; A contact hole formed in the interlayer dielectric layer; And a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, and a portion of the upper layer is exposed from the insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer. |
| priorityDate |
2015-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |