http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20160057516-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_33cf281df1fdf76b7da1bb88a75ba80d |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78606 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2014-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c528b51524d4504597555061f0211cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_866e0cab19cc62c656efcc9020f70ef6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06e95c45d28117ec6dd7d942cf6a52de http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_325748e8a4ff524b471c4dcfb22554f5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d37c6a19457b1bd8dc2c38dbe2c5d71c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72d83ae964331183f486b5c718e71f34 |
| publicationDate | 2016-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20160057516-A |
| titleOfInvention | thin film transistor array panel for digital X-ray detector and Method of thereof |
| abstract | The present invention provides a thin film transistor array substrate for a digital x-ray detector. The thin film transistor array substrate for a digital X-ray detector includes a thin film transistor, a common electrode layer, an interlayer insulating film, a ground electrode layer, a planarization film, and a lower electrode layer. The thin film transistor is located on the substrate and has a first semiconductor layer of oxide, a gate electrode, a first electrode and a second electrode. The common electrode layer extends from the first semiconductor layer and is made into a conductor. The interlayer insulating film is located on the thin film transistor and the common electrode layer. The ground electrode layer is located on the interlayer insulating film in the region corresponding to the common electrode layer. The planarizing film is positioned on the interlayer insulating film and the ground electrode layer and exposes the second electrode of the thin film transistor. The lower electrode layer is located on the planarization layer and is connected to the common electrode layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11011665-B2 |
| priorityDate | 2014-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.