http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20160042886-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ad856da99d5528ac0284a3ce4197ba19 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D3-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-123 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D5-48 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D5-34 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-48 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D3-38 |
| filingDate | 2013-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c03ddbd72e9e71aad69c1c4cd96e953 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a716a4f0ac475f2c253857a5ac48439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35b4a70cb53fd62643c8b672c099df8a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_877cf30f7a76131c86b929d46a4e2a3f |
| publicationDate | 2016-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20160042886-A |
| titleOfInvention | A method for microvia filling by copper electroplating with tsv technology for 3d copper interconnection at high aspect ratio |
| abstract | The present invention relates to a method for producing a silicon-on-insulator according to the present invention, comprising the steps of: preparing an electroplating solution of a copper methylsulfonate system; step 2: wetting microvias of the silicon penetration electrode technology through electroplating pretreatment; Diffusion is completed so that the copper ions and additive are reasonably distributed in the microvia surface and inside of the silicon via electrode technology; Step 4: connecting the wafer for silicon through electrode technology to the cathode of the power source; The current density of the plating condition is 0.01-10 A / dm 2 , and the temperature is 15-30 ° C. The current density of the plating condition is 0.01-10 A / dm 2 , Step 5: After electroplating, the wafer is thoroughly cleaned with deionized water and rotated or blown to dry Which relates to a method of filling micro-vias in high aspect ratio by a copper electroplating having a through-silicon electrode technology for the 3D interconnection of copper in. The microvia filling method by copper electroplating with a silicon penetration electrode technology for 3D copper interconnection at high aspect ratios provided in the present invention has a high via-filling rate and has a thin copper layer on the surface To achieve complete filling of the microvias with no aspect of voids and cracking, and having an aspect ratio of at least 10: 1, which is difficult to peel. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20200059309-A |
| priorityDate | 2013-08-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 61.