| abstract |
The vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source, and a channel between the source and the drain. The gate surrounds a portion of the channel. When the vertical transistor is an n-channel vertical transistor, the gate is configured to provide a compressive strain substantially along the channel extension direction, or when the vertical transistor is a p-channel vertical transistor, the gate substantially extends along the channel extension direction Tensile strain. In some embodiments, the vertical transistor may be configured to provide a tensile strain along the direction of extension of the channel when the vertical transistor is an n-channel vertical transistor, or may be configured such that when the vertical transistor is a p- RTI ID = 0.0 > ILD < / RTI > |