| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bcff13f8573db698307f919e6385d5c4 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L2207-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L2207-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00241 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0995
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-099
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0997
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-134
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-103
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-26 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-099
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00 |
| filingDate |
2014-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74df8cf74f9f82c685efad83d5e20f34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c7a8d9c7eed733a49f67dd3ec2038bbb |
| publicationDate |
2016-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20160013945-A |
| titleOfInvention |
Automatically placed-and-routed adpll with pwm-based dco resolution enhancement |
| abstract |
A method for controlling all digital digital phase-locked loops (PLLs) and PLLs is provided. The method includes receiving a reference signal (f REF ) in a controller and a time to digital converter (TDC), wherein the controller and the TDC are coupled to a plurality of tunable delay elements; Receiving a first signal input through a controller and a pulse width modulation (PWM) circuit in a plurality of tunable delay elements; Providing a PLL output (f DCO ) based at least in part on a first signal input to the TDC; And to the reference signal (f REF) and the PLL output (f DCO) the phase error output stage included, and the phase error output (Φ ERR) for generating a (Φ ERR) on the basis of the PLL output (f DCO) control As feedback to the controller. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10038451-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2602746-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/GB-2602746-A |
| priorityDate |
2013-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |