| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y40-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-201
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66469
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-068 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-775 |
| filingDate |
2013-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2015-04-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20150034232-A |
| titleOfInvention |
Non-planar semiconductor device having channel region with low band-gap cladding layer |
| abstract |
A non-planar semiconductor device having channel regions with low band gap cladding layers is described. For example, a semiconductor device includes a vertical configuration of a plurality of nanowires disposed on a substrate. Each nanowire includes an inner cladding layer having a first bandgap and an outer cladding layer surrounding the inner cladding layer. The cladding layer has a lower second band gap. The gate stack is disposed on the channel region of each of the nanowires and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on the cladding layer and surrounding the cladding layer, and a gate electrode disposed on the gate dielectric layer. The source and drain regions are disposed on either side of the channel regions of the nanowires. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11349035-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20190005692-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10693018-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20180067395-A |
| priorityDate |
2012-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |