| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bce787970b69aeb08d159e7c101c9ed7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7843
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31053 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-304
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2013-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7a0ebc90a47fac88ecdbe610b0cd34c5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca55b4358a85912f9721de17ddef7a85
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7dd97a2850f4af9521a64a4b9ef672b8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_560d61b9f15c5318d11c3f4f7012fb44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_621b2912540f8fca3cc01777dcbefbac
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08a2e6b701ecd58bd5e9b0cc3ddce316 |
| publicationDate |
2014-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20140114052-A |
| titleOfInvention |
Engineering dielectric films for cmp stop |
| abstract |
A method of forming an integrated circuit is provided. In one embodiment, the method includes forming a stop layer comprising carbon-doped silicon nitride on a gate region on a substrate, wherein the gate region comprises a poly gate and one or more spacers formed adjacent the poly gate And removing a portion of the first dielectric layer over the gate region using a CMP process, wherein the stop layer is formed by a CMP removal of the dielectric layer. ≪ RTI ID = 0.0 > Rate and a CMP removal rate that is less than or equal to the CMP removal rate of one or more of the spacers. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20170068309-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10411119-B2 |
| priorityDate |
2012-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |