http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20140048789-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8f823f036721e39c61ff0ced537273b8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c1e3d8364bf64e4ac6e1a9cd5df2bd54 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53271 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53209 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 |
| filingDate | 2013-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4d382307d0209cc8fecfe1acbae34a2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ba4b0e47b09ad205c4cd7e78308fc484 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5167e7e61270203b592d6372e756a2df |
| publicationDate | 2014-04-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20140048789-A |
| titleOfInvention | Semiconductor Structure and Formation Method thereof, SRAM Memory Unit, and SRAM Memory |
| abstract | The present invention relates to a semiconductor structure and a method of forming a semiconductor structure, an SRAM memory unit, and an SRAM memory. The semiconductor structure of the present invention includes at least two adjacent transistors, a conductive layer, and at least two adjacent transistors are formed on a semiconductor substrate; A doped region located between the gate electrode of two mutually adjacent transistors and the gate electrode of two mutually adjacent transistors is surrounded to form an opening; The conductive layer covers the bottom and sidewalls of the opening. Another semiconductor structure includes a first transistor and a second transistor, a conductive layer, wherein the first transistor and the second transistor are formed on a semiconductor substrate; The insulating layer of the gate electrode of the first transistor covers only a part of the gate electrode layer remote from the second transistor doped region; An insulating layer, a gate electrode layer of the first transistor exposed by the insulating layer, a doped region of the second transistor, and a gate electrode of the second transistor are surrounded to form an opening; The conductive layer covers the bottom and sidewalls of the opening. The present invention further provides a method of forming the semiconductor structure, an SRAM memory unit comprising the semiconductor structure, and an SRAM memory. According to the present invention, the area of the semiconductor structure can be reduced. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9721956-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10276580-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9978755-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20150131915-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10833090-B2 |
| priorityDate | 2012-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID57350325 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID447604988 |
Total number of triples: 32.