http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20130143029-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c5520dd38cc403678d9f91e0b0ee95fb |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1251 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78645 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368 |
| filingDate | 2011-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f71e0620a0dcea641bd4f76e532f2e6 |
| publicationDate | 2013-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20130143029-A |
| titleOfInvention | Thin film transistor substrate, manufacturing method thereof, display device |
| abstract | The active matrix substrate 20a includes an insulating substrate 10a, a first gate electrode 11b formed on the insulating substrate 10a, and a first oxide semiconductor layer 13a having a first channel region Ca. A first thin film transistor 5a provided on the insulating substrate 10a and having a second gate electrode 11c and a second oxide semiconductor layer 13b having a second channel region Cb. The second thin film transistor 5b and the second gate insulating film 17 covering the first oxide semiconductor layer 13a and the second semiconductor layer 13b are provided. The third gate electrode 25 is disposed on the second gate insulating layer 17 to face the first channel region Ca and the second channel region Cb via the second gate insulating layer 17. Is formed. |
| priorityDate | 2010-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 48.