| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-00 |
| filingDate |
2011-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b060ac075fcc18dbe3285dbef175b604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_036bdbcdce7c17642fcd3538acfbf598 |
| publicationDate |
2012-08-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20120087711-A |
| titleOfInvention |
Semiconductor integrated circuit and control method thereof |
| abstract |
The semiconductor integrated circuit includes a first chip and a second chip stacked on the first chip, the first memory area being formed on the second chip, and the first chip repairing a defect of the first memory area on the first chip. 2 memory regions are formed. |
| priorityDate |
2011-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |