| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-318
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2010-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f3deb72298cacbee76ab89633f81c1e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca9a9b00a27c7273ca5270e12720cf10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c512ca65210c734f7332ec270a7cafd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4aab1122f6a1a5b6aa0f9096b424b5e1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d129519023af369b410942874b1b7062
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68b2ecfb5b0e8274c61803b8d2034a37 |
| publicationDate |
2011-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20110101876-A |
| titleOfInvention |
A semiconductor device having a buried bit line and a manufacturing method of the semiconductor device |
| abstract |
A semiconductor device including buried bit lines and vertical pillar transistors having a low resistance and a method of manufacturing the same are disclosed. The vertical pillar transistor is formed on a substrate and includes a body having a lower portion and an upper portion, a source / drain node disposed over the body, and a drain / source node disposed under the body. The semiconductor device is formed at least on an upper surface of the lower portion of the body, and includes a buried bit line including metal silicide and a word line partially enclosing the upper portion of the body. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8836001-B2 |
| priorityDate |
2010-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |