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filingDate 2007-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2010-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20100034033-A
titleOfInvention Semiconductor memory and system
abstract The pair of access control circuits in which the bit line pairs are wired correspond to the same data terminal and are assigned different addresses. The data exchange circuit prohibits the replacement of a pair of data terminals and a pair of data lines when one side of the access control circuit is used during the test mode, and a pair of data terminals and a pair of data when the other side of the access control circuit is used. Replace the wire connections. This makes it possible to give data signals of the same logic level to bit lines having different logics without changing the logic of the data signals supplied to the data terminals. Stress can be applied between a contact disposed between a pair of access control circuits and a bit line adjacent to both sides of the contact. As a result, a test pattern can be designed easily, and test efficiency can be improved.
priorityDate 2007-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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