| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-9202
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-80896
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate |
2008-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1a529dbab16473ebc49ee9525de217d9 |
| publicationDate |
2009-12-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20090126077-A |
| titleOfInvention |
Memory semiconductor device and manufacturing method thereof |
| abstract |
The present invention relates to a memory semiconductor device and a method of manufacturing the same. The memory semiconductor device according to the present invention electrically connects a memory substrate on which memory transistors are formed, a peripheral circuit board on which peripheral circuit transistors are formed, an adhesive layer interposed between the memory substrate and the peripheral circuit boards, and the memory transistors and the peripheral circuit transistors. Contains a linking structure to connect. The memory substrate is used as an active region of the memory transistors and includes vertical active pillars having a source region, a channel region, and a drain region. |
| priorityDate |
2008-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |