http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20090068571-A
Outgoing Links
Predicate | Object |
---|---|
assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1146d1dc4ffd66d77c25805ca3f9a74f |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 |
filingDate | 2007-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2a5fc3352e9c0eef3b14943493ebacff |
publicationDate | 2009-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | KR-20090068571-A |
titleOfInvention | Semiconductor device having multilevel interconnections and method for manufacturing the same |
abstract | Provided are a semiconductor device including a via contact obtained from a conductive polymer, and a method of manufacturing the same. The device electrically connects a first wiring layer formed on a semiconductor substrate, a second wiring layer formed on the first wiring layer, an interlayer insulating film interposed between the first wiring layer and the second wiring layer, and the first wiring layer and the second wiring layer. The via contact includes a via contact including a conductive polymer plug formed through the interlayer insulating layer so as to be connected thereto. Therefore, the first wiring layer and the second wiring layer are electrically connected to each other by a via contact including a conductive polymer plug formed through the interlayer insulating film interposed between the first wiring layer and the second wiring layer constituting the multilayer wiring structure. The via hole can be gapfilled with excellent buried characteristics without voids such as voids in the via hole, and the resistance of the conductive polymer plug can be reduced even when the via hole is a hole having a small inlet size and a large aspect ratio. It can be advantageously applied to implement low resistance wiring of the device. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8516689-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9184063-B2 |
priorityDate | 2007-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.