http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20080088972-A

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filingDate 2007-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9b0f8d18cc8b884b6ee03bd2e63029e8
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publicationDate 2008-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20080088972-A
titleOfInvention Failure analysis method of semiconductor chip
abstract The failure analysis method of a semiconductor chip is a failure chip in a BGA type package including a decapped FBGA package in order to proceed with failure analysis according to a current. A defect analysis method of a semiconductor chip for performing a defect analysis, the method comprising: encapsulating a rear surface of a defective chip in the decap package with a protective material; Grinding the top surface of the package including the bad chip encapsulated with the back surface such that a bonding pad of the bad chip is exposed; Applying a voltage for failure analysis by using a probe card to the bonding pad of the broken and exposed bad chip; And detecting the type of the defect by detecting whether the defective chip is operated according to the applied voltage.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115639460-A
priorityDate 2007-03-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 21.