http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20080030386-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2006-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e3d3f36374d75d24b1affc1bc33e054 |
| publicationDate | 2008-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20080030386-A |
| titleOfInvention | Manufacturing method of semiconductor device |
| abstract | The present invention discloses a method for fabricating a semiconductor device capable of preventing shorts between gates and bit line contacts. The disclosed method of the present invention comprises a contact hole for a landing plug, which is divided into a cell region and a peripheral region, and defines a landing plug forming region of the cell region on a semiconductor substrate having a gate and a junction region having a spacer in each region. Forming a first interlayer dielectric layer; forming a landing plug in the landing plug contact hole; forming a second interlayer dielectric layer on the entire surface of the substrate including the landing plug; Etching the second interlayer insulating film until the junction region of the gate and the upper side portion of the gate are exposed to form first contact holes defining the bit line contact forming regions of the peripheral region, and both sides of the first contact hole; Forming a bit line contact spacer on a wall; and etching the second interlayer insulating layer to define a bit line contact forming region of the cell region. Forming a barrier layer on the second interlayer insulating layer including a tack hole, a surface of the second contact hole, and a bit line contact spacer in the peripheral region; and filling the first and second contact holes in which the barrier layer is formed. And forming a conductive film for bit line contact on the barrier film. |
| priorityDate | 2006-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.