http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20080029311-A
Outgoing Links
Predicate | Object |
---|---|
assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-485 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
filingDate | 2006-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8c1ba37e6a09b233ad902e887f12de6c |
publicationDate | 2008-04-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | KR-20080029311-A |
titleOfInvention | Bit line patterning method of semiconductor device |
abstract | SUMMARY OF THE INVENTION The present invention provides a bit line patterning method of a semiconductor device which can prevent the occurrence of bowing in the middle part or the top of the bit line while taking the profile of the bit line hard mask vertically. A bit line patterning method of a device may include stacking barrier metal, a metal electrode, and a bit line hard mask in sequence; Etching the bit line hard mask; Forming a capping layer on the entire surface including the bit line hard mask; Etching the metal electrode using the capping layer as an etch barrier; Isotropically etching the metal electrode and the barrier metal; And removing the capping layer, wherein the present invention includes the step of performing a capping layer process after etching the bit line hard mask to reinforce the top portion of the bit line hard mask so that the bit can be etched during subsequent etching of the metal electrode. The profile of the line hard mask can be taken vertically, and the etching margin can be increased even during the etching process of the metal electrode. |
priorityDate | 2006-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.