http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20080002539-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b1007735376d07808ebe297f823b2829 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F2202-104 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1333 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136 |
| filingDate | 2006-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17d5e67ab73d44d6384a00337f633a67 |
| publicationDate | 2008-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20080002539-A |
| titleOfInvention | Manufacturing method of polysilicon thin film transistor and manufacturing method of liquid crystal display device using same |
| abstract | The present invention relates to a method of manufacturing a polysilicon thin film transistor to simplify the process by minimizing the number of times the exposure mask is used, and a method of manufacturing a liquid crystal display device using the same, in particular, a method of manufacturing a polysilicon thin film transistor is amorphous on a substrate Forming a silicon layer, forming a first self-aligned layer on a predetermined portion of the amorphous silicon layer, and forming a first metal layer on the amorphous silicon layer exposed between the first self-aligned layer And removing the first self-aligned layer, etching the amorphous silicon layer using the first metal layer as a mask, to form a semiconductor layer, and forming the amorphous silicon layer using the first metal layer as a catalyst. Crystallizing, forming source / drain electrodes on both sides of the polysilicon layer, and Characterized in that comprises a step of forming a gate insulating film on the front electrode and including a lane, the method comprising: forming a gate electrode on the gate insulating film between the source electrode and the drain electrode. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102365710-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8143670-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2010117201-A2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2010117201-A3 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8324689-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109712933-A |
| priorityDate | 2006-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.