| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5621 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3454 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate |
2004-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09c77ad624526beae545eb4bf3a9b170 |
| publicationDate |
2007-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20070087118-A |
| titleOfInvention |
Nonvolatile Semiconductor Memory Device |
| abstract |
A page mode multi-level NAND type memory utilizes two different verify levels per data state, and is connected to a memory cell, and is a first data storage circuit for storing data of an externally input first logic level or second logic level. ; A second data storage circuit connected to the memory cell and storing data of a first logic level or a second logic level read from the memory cell; And a control circuit for controlling the memory cell and the first and second data storage circuits, reproducing externally input data, and writing data into the memory cells. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101150645-B1 |
| priorityDate |
2003-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |