http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20070068667-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
| filingDate | 2005-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34075a08e1c8ab29cbd98fe4622cc03f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d1046c63663b718844191bf05f3183c |
| publicationDate | 2007-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20070068667-A |
| titleOfInvention | Device Separation Method of Semiconductor Device |
| abstract | The present invention is to provide a method for manufacturing a device isolation film of a semiconductor device capable of preventing the generation of voids and peaks of the device isolation film, the present invention is to etch a semiconductor substrate to a predetermined depth to the top of the trench having an etched slope shape Forming a region, forming a spacer insulating layer on the entire surface including the upper region of the trench, and etching the semiconductor substrate under the upper region to a predetermined depth to form a lower region of the trench having an etched vertical shape And forming a device isolation layer buried in the trench, and forming a recess pattern for the recess gate by etching the active region defined by the trench to a predetermined depth. It is possible to secure high quality transistor characteristics by preventing the voids formed in the bottom of the separator and the bottom of the recess. It has the effect of device implementation and can reduce costs given to assist in improved productivity and improving the device characteristics, design secure, high integration of semiconductor devices is possible to maximize the gain process margin, yield, production costs down. |
| priorityDate | 2005-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.