http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20070041161-A

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filingDate 2005-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2007-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20070041161-A
titleOfInvention Calibration method of semiconductor test device and semiconductor test device
abstract The calibration method of a semiconductor test apparatus including N (N is a natural number of 2 or more) drivers and N comparators includes: a first delay path coupled to one of the N drivers, and N N of the first calibration board. First skews between the first signals due to the N third delay paths for the N first signals transmitted over the two delay paths and the N third delay paths coupled to the N comparators Calculating, and N fourth delay paths coupled to the N drivers, N fifth delay paths of a second calibration board, and N second signals transmitted through the N third delay paths. Calculating second skews between the second signals due to the N fourth delay paths using first skews between the first signals. The timing skew of clock signals can be measured and corrected for drivers and comparators on N channels at once. Therefore, the time taken to perform calibration of the semiconductor test apparatus having a plurality of drivers and a plurality of comparators corresponding to the plurality of channels can be greatly reduced.
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