http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20070036496-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-762 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09bb2705681468549846a402a5d94fdd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d1046c63663b718844191bf05f3183c |
| publicationDate | 2007-04-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20070036496-A |
| titleOfInvention | Method for manufacturing a semiconductor device having a tapered trench |
| abstract | SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device capable of preventing voids of a gap fill insulating film gap-filled in a device isolation trench and at the same time ensuring bottom flatness of a recess pattern. Etching the semiconductor substrate to a predetermined depth to form an upper region of the trench having an etched tapered shape, and etching the semiconductor substrate below the upper region to a predetermined depth to form a lower region of the trench having an etched shape close to a vertical position Forming a recess, forming a device isolation layer buried in the trench, and forming a recess pattern for a recess gate by etching the active region defined by the trench to a predetermined depth.n n n n Recess gate, recess pattern, trench, STI, profile angle, tapered etching |
| priorityDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.