| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36d1d9c59848bff6ad5f55923d1290f5 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48137
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-2022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73253
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-49175
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0862
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32145 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1068
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0893
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0888 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 |
| filingDate |
2006-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_99a6efb12d753052b87fc847a08fdeba |
| publicationDate |
2006-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20060120501-A |
| titleOfInvention |
Memory modules, memory systems, and information devices |
| abstract |
It provides a memory system including a ROM and RAM of the storage capacity is easy to use.n n n The memory system includes a nonvolatile memory, a cache memory, a control circuit, and an information processing device. The data in the nonvolatile memory is transferred to the cache memory and held for high speed. When the data of the nonvolatile memory is transferred to the cache memory, error correction is performed and reliability is improved. It is possible to access the cache memory and the nonvolatile memory independently from the information processing apparatus, thereby improving the convenience of use. A memory system composed of these plural chips is configured as a memory system module in which each chip is stacked on each other and wired by ball grid array (BGA) and bonding between chips. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10078448-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101056560-B1 |
| priorityDate |
2005-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |