http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20050071060-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_efd77c1983329ca444312479161a8c18 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7682 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 |
| filingDate | 2003-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a6936c6c986797cf52fec141dcbc5c1d |
| publicationDate | 2005-07-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20050071060-A |
| titleOfInvention | Semiconductor device and method for the same |
| abstract | SUMMARY To provide a semiconductor device having a low capacitance and an interlayer insulating film, and a method of manufacturing the same, the present invention includes forming a first interlayer insulating film over a lower insulating film over a semiconductor substrate on which individual devices including a lower metal wiring layer are formed; Selectively etching the first interlayer insulating film to form a first interlayer insulating film pattern; Depositing a nitride film on the first interlayer insulating film pattern, and selectively etching the nitride film on the first interlayer insulating film pattern to form spacers on sidewalls of the first interlayer insulating film pattern; Forming a first oxide film filling a spacer on the first interlayer insulating film pattern; Etching the upper portion of the first oxide layer to form a second interlayer insulating layer having the upper portion of the spacer exposed; Etching the exposed spacers to form open pores in a second interlayer insulating film, and then forming a third interlayer insulating film to form an air gap formed of discarded holes between upper and lower metal wiring layers; And selectively removing the interlayer insulating layer to form a via hole exposing the lower metal wiring, filling the inside of the via hole with a metal material, and then forming an upper metal wiring layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9379118-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9214374-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8736018-B2 |
| priorityDate | 2003-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.