http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20050057786-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate | 2003-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_09c6ead0e6a7df9f0a12530f28651005 |
| publicationDate | 2005-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20050057786-A |
| titleOfInvention | Method of manufacturing flash memory device |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device. In a flash memory device employing a self-aligned shallow trench isolation scheme (SA-STI scheme), a floating gate is formed such that a lower portion has a high impurity concentration and a lower portion has a low impurity concentration. Since the first polysilicon layer is formed, the first polysilicon layer having the positive slope profile in the device isolation etching process has the vertical profile or the negative slope profile due to the faster oxidation rate as the impurity concentration is higher during the month oxidation process. The gate bridge phenomenon caused during the gate etching process can be prevented without damaging the oxide layer. |
| priorityDate | 2003-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 14.