| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0466
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0425
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0416 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42332
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-14 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 |
| filingDate |
2003-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ba8672a8592aa5b11bb1b86165a7770
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74e5bb8590ed337dc24aa09c5471c891
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d972fdf1c69481dddc69001e7c485f0c |
| publicationDate |
2005-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20050055197-A |
| titleOfInvention |
Erasing methods of a non-volatile memory device including discrete charge trap sites |
| abstract |
Methods of erasing a nonvolatile memory device having discontinuous charge trap sites between a semiconductor substrate and a gate are provided. This method applies a negative voltage to a gate that overlaps a semiconductor substrate with a charge storage layer providing a discrete charge trap site. A first positive voltage is applied to the source formed in the semiconductor substrate at one end of the gate. A second positive voltage equal to or lower than the first positive voltage is applied to a drain formed in the semiconductor substrate at the other end of the gate. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7940567-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8462558-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7778083-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7813183-B2 |
| priorityDate |
2003-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |