http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20050009574-A

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6f1cdac90c4272d2ed510122d7153738
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76294
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
filingDate 2003-07-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_954d58471b83b9c5da8ee463149eb246
publicationDate 2005-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20050009574-A
titleOfInvention Method for forming a trench in semiconductor device
abstract The present invention relates to a method for forming a trench in a semiconductor device, wherein a pad oxide film and a pad nitride film are sequentially patterned, a trench is formed by performing an etching process using the pad nitride film as an etching mask, and a selective epitaxial growth (SEG). A silicon oxide film is formed on the inner wall of the trench to have the same thickness irrespective of the pattern size of the trench, so that a top corner is formed uniformly regardless of the trench pattern size. A method of forming a trench in a semiconductor device in which a double slope is not generated in a trench inner wall is disclosed.
priorityDate 2003-07-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
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http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID457707758
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419579069

Total number of triples: 16.