http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20040105061-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-1201 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50012 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 |
| filingDate | 2003-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74cfcd8d2e135357a929e531c2b9227b |
| publicationDate | 2004-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20040105061-A |
| titleOfInvention | A semiconductor memory device with bypass circuit for evaluating character of internal clock signal |
| abstract | A semiconductor memory device having a bypass circuit for verifying characteristics of an internal clock signal is disclosed. A semiconductor memory device having a bypass circuit for verifying characteristics of an internal clock signal according to the present invention is characterized by including a data output circuit, a data input circuit, a first bypass circuit, and a second bypass circuit. . The data output circuit outputs the output data output from the internal circuit to the input / output pad in synchronization with the output clock signal. The data input circuit outputs input data received from the outside through the input / output pad to the internal circuit in synchronization with the input clock signal. The first bypass circuit bypasses the output clock signal to the input / output pad in response to the first control signal. The second bypass circuit bypasses the input clock signal to the input / output pad in response to the second control signal. When either one of the first bypass circuit and the second bypass circuit operates, the data output circuit and the data input circuit stop operation. A semiconductor memory device having a bypass circuit for verifying characteristics of an internal clock signal according to the present invention has an advantage of easily verifying characteristics of an internal clock signal in a packaged state. |
| priorityDate | 2003-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID454197119 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID73093 |
Total number of triples: 20.