| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7887
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42332 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate |
2003-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6fb4a4b08544b586c93a96470f0d8ac5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_460e2e57dbc246f84b32cdd8ca9a529f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89d854c843dc23703b6c9d1a08b77fdd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b48de73aa79c7b5ecc26375101c111c3 |
| publicationDate |
2004-12-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20040099802-A |
| titleOfInvention |
SONOS memory device having nanocrystal layer |
| abstract |
Disclosed is a Sonos memory device having a nano-sized crystal layer. The disclosed sonos memory device is a sonos memory device including a memory transistor having a gate having a sono gate structure on a semiconductor substrate, and the gate includes a tunneling oxide film and a trap site for trapping charge passing through the tunneling oxide film. The memory node layer and the gate electrode are sequentially stacked, and the memory node layer includes a crystal layer made of crystals having nano size and spaced apart from each other for trapping of the charge. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20060095819-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100806788-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100806087-B1 |
| priorityDate |
2003-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |