| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7923
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate |
2003-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67dde1a134d50020683d26fe6c529a1a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a95ce326042ee60d42035aa06e2b7149
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9383a18c5601bf774128a579568de171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0bef65fce9904763091807444d2ac752
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6ef768612a0d620d5c4c61a9a3d45695 |
| publicationDate |
2004-10-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20040085663-A |
| titleOfInvention |
Method for manufacturing SONOS memory device with twin-ONO by reverse self-aligning process |
| abstract |
A method of manufacturing a SONOS memory device having a twin-ONO type using a reverse self-aligning process is provided. The manufacturing method according to one aspect of the present invention proposes a method in which the ONO dielectric layer is formed in a physically spaced form by an inverse magnetic matching method at the same time without being limited by the limitation of photo lithography. . Spacers are introduced to set the width of the buffer layer and the ONO dielectric layer to introduce the inverse magnetic matching scheme. Accordingly, twins that artificially limit the distribution of charge trapped during programming and erasing of SONOS memory devices to improve device characteristics, and at the same time artificially limit the spreading of charges after program / erase over time. 2-bit SONOS nonvolatile memory device can be manufactured. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100796090-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7618864-B2 |
| priorityDate |
2003-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |