http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20040077284-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28052 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26506 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-265 |
| filingDate | 2003-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b92f20a446f81fd2e91c90bf2ecfda5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d5d4d17dfe5950ac673ed60199a4343 |
| publicationDate | 2004-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20040077284-A |
| titleOfInvention | Method of fabricating a surface-enlarged gate and a semiconductor device thereof |
| abstract | An extended gate having an enlarged upper area, a semiconductor device having the same, and a method of manufacturing the same are disclosed. In order to manufacture a semiconductor device having an extended gate, a gate poly is first formed on a semiconductor substrate, and then an insulating film is deposited on the entire surface of the substrate. Subsequently, the upper surface of the insulating film is removed to be positioned below the upper surface of the gate pattern. After forming a conductive film formed of polysilicon on the entire surface of the substrate, a spacer formed of polysilicon is formed on the gate poly by removing it by anisotropic etching. By removing the insulating film using the spacer as a mask, a parasitic capacitor adjusting member is formed at the lower side of the gate poly at the bottom of the spacer. A low concentration source / drain region is formed using the spacer, the gate poly, and the parasitic capacitor adjusting member as a mask. After the nitride film is formed on the entire surface of the substrate, a nitride film spacer is formed and a high concentration source / drain region is formed using the nitride film spacer as a mask. Therefore, the contact area between the gate poly and the silicide film can be increased, and the parasitic capacitance formed between the gate poly and the substrate can be effectively controlled. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100660278-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103681290-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100890383-B1 |
| priorityDate | 2003-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.