Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-0836 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-141 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-203 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-0624 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-05 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-08 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-06 |
filingDate |
2003-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d6b2fb678a776bf42eaab50e0cac166 |
publicationDate |
2004-08-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
KR-20040072963-A |
titleOfInvention |
Multi-process a/d converter in which output synchronization among the processes is corrected |
abstract |
The present invention relates to a multi-process A / D converter, which generates delayed clock signals having different delay times according to phase differences by feeding back the output of each path and detecting a phase, and using the delayed clock signals. It characterized in that to correct the output of.n n n According to the multiple A / D converter according to the present invention, by using the delayed clock signal to correct the error itself caused by the signal is synchronized with the clock signal, it is possible to reduce the distortion of the signal by correcting the output of each path. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100824796-B1 |
priorityDate |
2003-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |