http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20040063191-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01D11-245 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01F15-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01F15-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N23-50 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 |
| filingDate | 2003-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f36d8f042e2d7ee332d0ecce6360a3e6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6611393c23b10eef5254e6e10e9f03f0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32db21413455af7285f83dd48551a790 |
| publicationDate | 2004-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20040063191-A |
| titleOfInvention | Parallel bit test method and semiconductor memory device having parallel bit test funtion thereof |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a parallel bit test function for outputting parallel bit test data to prevent a failure from being generated under the same control in a normal memory device and a test mode in a semiconductor memory device.n n n A semiconductor memory device having a parallel bit test function according to an embodiment of the present invention includes a clock generator for receiving a clock signal CLK and generating a first clock signal CLK1 for outputting normal mode data by a control signal Control. A plurality of input / output sense amplifiers for sensing and amplifying and outputting data pairs respectively read from the memory cells, and first data generated from the clock generator by inputting each pair of data sensed and amplified from the plurality of input / output sense amplifiers. A plurality of drivers for outputting data by the clock signal CLK1, a plurality of comparators for comparing the data output from a pair of drivers among the plurality of drivers, and outputting a match determination signal; Output test data by ORing the match decision signal output from a pair of comparators of Is a plurality of test data output units, a plurality of first MUXs for latching data output from one of the plurality of drivers, and selectively outputting the latched normal data by a normal mode selection signal, and the plurality of tests. A plurality of second MUXs for latching test data output from the data output units and outputting the latched test data by a test mode selection signal, and normal data selected and output from the first MUXs or the second MUXs; It includes a plurality of data output buffer for receiving the test data, buffered and output. |
| priorityDate | 2003-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.