| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-943
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-962 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K19-202
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K85-221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K19-00 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L51-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L51-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B82B1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate |
2002-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a8f400e2f5f133c9bcd5625cc1383462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9972fd1612c5d1392766cf7208eb21fe |
| publicationDate |
2004-07-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20040060370-A |
| titleOfInvention |
Memory utilizing vertical nanotube |
| abstract |
A memory using vertical nanotubes is disclosed. The disclosed memory includes a first electrode array formed in a stripe pattern, a dielectric layer stacked on the first electrode array and arranged with a plurality of holes, a vertical growth into a hole of the dielectric layer in contact with the first electrode array and emitting electrons. A nanotube array, a second electrode array formed in a stripe pattern on the dielectric layer to be in contact with the nanotube array and orthogonal to the first electrode, and to capture electrons emitted from the nanotube array on the second electrode array. And a gate electrode stacked on top of the memory cell and forming an electric field around the nanotube array. Highly integrated memory can be implemented. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100674144-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100745769-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100843336-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8558303-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8063430-B2 |
| priorityDate |
2002-12-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |