http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20040005512-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76227 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate | 2002-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb60458f72371b3e07df30315b758bf7 |
| publicationDate | 2004-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20040005512-A |
| titleOfInvention | Method for forming the Isolation Layer of Semiconductor Device |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a device isolation film of a semiconductor device. In particular, an amorphous silicon layer is formed after removing a nitride film on a silicon substrate during formation of a device isolation film by a shallow trench isolation (STI) process. Stacked and etched to form an amorphous spacer on the upper sidewall of the device isolation layer, thereby oxidizing the width of the device isolation layer above the active region, thereby forming excessive etching of both edges of the device isolation layer by subsequent etching and cleaning processes. It is a technology that can prevent the shape of the moat to improve the characteristics and reliability of the semiconductor device, thereby enabling high integration of the semiconductor device. |
| priorityDate | 2002-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 16.