http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20030044445-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2001-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d48a72790c2e1138e898e7d33648351d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c184caa5d82e1840d3289416b9222b5 |
| publicationDate | 2003-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20030044445-A |
| titleOfInvention | Semiconductor and fabricating method of the same |
| abstract | The present invention relates to a method for manufacturing a semiconductor device, and in particular, to provide a semiconductor device and a method for manufacturing the same, which are suitable for preventing the deterioration of device characteristics due to the short channel effect in the transistor manufacturing process according to the high integration, the present invention Silver, a substrate; A gate electrode provided on the substrate; Source / drain impurity regions provided in the substrate; And an insulating film disposed along an interface between the impurity region and the substrate except for a region in contact with a channel.n n n In addition, the present invention comprises the steps of forming a sacrificial insulating film pattern on a predetermined gate electrode region on the substrate; Isotropically etching the substrate using the sacrificial insulating layer pattern as an etching mask; Forming an insulating film along a profile of the etched substrate surface to expose a portion of the substrate under the sacrificial insulating pattern; Forming a conductive layer for source / drain formation on the entire structure of the insulating layer; Planarizing the conductive layer to expose the surface of the substrate under the sacrificial insulating pattern and removing the sacrificial insulating pattern; And sequentially forming a gate insulating film and a gate electrode in the predetermined gate electrode region. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100783188-B1 |
| priorityDate | 2001-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.