http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20030001131-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2001-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed1e580dd67ba1e9172590c6909c9b5b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c184caa5d82e1840d3289416b9222b5 |
| publicationDate | 2003-01-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20030001131-A |
| titleOfInvention | A forming method of contact |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a contact forming method using a photoresist for argon fluoride. In the present invention, when the pattern is formed by using an ArF-only resist during the self-aligned contact process, a narrow pattern is formed by preventing the pattern deformation generated in the etching process and the notch due to the lack of PR margin using the TLR structure. It is an object of the present invention to provide a method for forming a contact that can be made. To this end, the present invention comprises a first step of sequentially forming an interlayer insulating film, a photoresist sacrificial film and a hard mask on a substrate having a plurality of neighboring gate electrodes; Forming a photoresist pattern on the hard mask; Selectively etching the hard mask and the photoresist sacrificial layer to define a contact formation region; A fourth step of forming a contact hole exposing the surface of the substrate between the gate electrodes by selectively etching the interlayer insulating layer using the hard mask and the photoresist sacrificial layer as a mask; And a fifth step of forming a plug embedded in the contact hole. |
| priorityDate | 2001-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.