| abstract |
Provided is a method of forming a cell array of a memory device having a plurality of tunnel junction barrier layers and a unit cell composed of two shrinkable transistors, the size of which is as small as 4F 2 . Here, "F" represents the minimum size, i.e., the line width of the data lines or the write lines (word lines or control gate lines) or the gap therebetween. This method has a feature designed to have variety in terms of setting the type and thickness of the material film as well as excellent surface flatness. In addition, this manufacturing process has the advantage that the cell array region and the peripheral circuit region is formed at the same time, thereby reducing the total number of processes significantly. The trench isolation layer, source / drain regions and gate regions of the peripheral circuit are formed simultaneously with the regions in the cell array corresponding thereto. |