http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20020094596-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
| filingDate | 2001-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_827c6762554753d896897dd9b572aa4c |
| publicationDate | 2002-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20020094596-A |
| titleOfInvention | A method for fabricating trench of semiconductor device |
| abstract | The present invention discloses a method of forming shallow trench isolation in a semiconductor device.n n n A trench forming method of a semiconductor device of the present invention disclosed is a step of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate, applying a mask pattern having a predetermined size on the second insulating film, and applying a 370 to 900 W to the semiconductor substrate. Forming a shallow trench having a rounded shape at the bottom and side by applying a bias power to a predetermined depth of the substrate, forming a fourth insulating layer to fill the inside of the shallow trench; Planarizing the insulating film. |
| priorityDate | 2001-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419579069 |
Total number of triples: 13.