http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20010070233-A

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filingDate 2000-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2001-07-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20010070233-A
titleOfInvention Burst mode flash memory
abstract The clock generator responsive to the external output enable signal generates a delayed internal clock signal to improve the reliability of the data output from the flash memory. The clock trigger generator circuit decodes the address signal, thereby generating an internal clock signal to reduce the delay time of data output according to the external clock signal. A bypass signal is provided to disable the clock trigger generator circuit. The output circuitry provides a bypass data path to further reduce the delay time of the data output into the burst mode flash memory. Decoder counter interrupt circuitry provides a "look ahead" address decoding scheme to reduce the time required to output data.
priorityDate 1999-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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