http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20010037892-A

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0234
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
filingDate 1999-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7655644c027898b5cc88a8d917878a7d
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publicationDate 2001-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20010037892-A
titleOfInvention Method for formation of metal line in semiconductor device
abstract The present invention relates to a method for forming a metal wiring in a highly integrated semiconductor device using a multi-layered metal wiring, and more particularly, using a spin on glass (SOG) film and an O 3 -TEOS [Si (OC 2 H 5 ) 4 ] film. The present invention relates to a method of forming a metal wiring to obtain improved flatness and uniformity by forming an interlayer insulating film between metal multilayers. O 3 of, (a normal pressure vapor deposition method Atmospheric Pressure Chemical Vapor Deposition) - The invention of claim After completion of the formation of the first metal wire coated with a first metal interlayer insulation film, and the coating since SOG (Spin On Glass), and curing APCVD It is composed of forming a contact hole by applying TEOS after exposure and etching, and according to the present invention can prevent the bowing of the contact hole, and the metal wiring is corroded by moisture containing SOG. Can be prevented, and an improved planarization can be achieved without an additional planarization process, thereby facilitating the subsequent process.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100419746-B1
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priorityDate 1999-10-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 30.