http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20010029924-A

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publicationDate 2001-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-20010029924-A
titleOfInvention Data processing apparatus
abstract Each of the plurality of buses 10 corresponds to a local buffer 13 to a local buffer 15, and the transmission speed is based on the difference in the bit widths of the bus 1 and the buses 10 to 12. Input / output of data is performed between the bus 1 and each of the buses 10 to 12 so as to absorb the speed difference. When the bandwidth to be allocated to the master device 4 to the master device 6 is to be changed, the master device 4 to the master device 6 and the buses 10 to 12 and the local buffers 13 to local are used. It is not necessary to redesign the memory device, the memory controller 3, and the bus 1 because the read / write port of the buffer 15 can be changed.
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Total number of triples: 27.