http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20010029812-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f481982f9992cbb527a6d31589832958 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2000-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c5210736cc92671218041e0dc71ab3f7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b09d7c44a7669acd394f0a00eef8b2c |
| publicationDate | 2001-04-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20010029812-A |
| titleOfInvention | A CMOS integrated circuit having vertical transistors and a process for fabricating same |
| abstract | The process for fabricating a CMOS integrated circuit with a vertical MOSFET device is described. In the process, at least three material layers are sequentially formed on the semiconductor substrate. The three layers are arranged such that the second layer is inserted between the first and third layers. The second layer is sacrificial and is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET device.n n n After at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form n-type and p-type regions in the structure. A window or trench is formed in the layers of both the n-type region and the p-type region. The window terminates at the surface of the silicon substrate on which either the source or drain region is formed. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore, the crystalline semiconductor plug is doped to form source extension, drain extension, and channel region in the plug. Subsequent processing forms the other of the source or drain on top of the vertical channel and removes the sacrificial second material layer. Removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. A device gate dielectric is then formed in the exposed portion of the doped semiconductor plug. Subsequently, a gate electrode is deposited. The physical gate length of the resulting device corresponds to the deposition thickness of the second material layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100922557-B1 |
| priorityDate | 1999-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 44.