http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20010006800-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38520f366e74704305b34fb93a81121e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-133 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0818 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-18 |
| filingDate | 2000-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e398a21f3271e3131327178af50797bc |
| publicationDate | 2001-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20010006800-A |
| titleOfInvention | Internal clock generating circuit |
| abstract | An object of the present invention is to provide an internal clock generating circuit which can suppress an increase in chip area while reducing a delay step of a delay line and can generate an internal clock in a wider frequency range. The internal clock generation circuit includes a phase comparator 302, a shift register 303, a filter 304, a monitor circuit 305, a plurality of delay lines, for example, first and second delay lines 300 and 301, and an input buffer. 306 and a driver 307. Here, the first and second delay lines 300 and 301 have different delay steps, respectively, and the first delay line 300 has a larger delay step than the second delay line 301. |
| priorityDate | 1999-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.