http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20000076758-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7397 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66734 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66348 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L31-062 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate | 2000-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2000-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20000076758-A |
| titleOfInvention | Mos-gated device having a buried gate and process for forming same |
| abstract | An improved trench MOS-gateed device includes a single crystal semiconductor substrate, on which a doped top layer is disposed. The top layer includes a plurality of heavily doped body regions on the top surface that have a first polarity and cover the drain regions. The top layer also includes a plurality of heavily doped source regions on the top surface opposite the body region and having a second polarity. The gate trench extends from the upper surface of the upper layer to the drain region and separates the source region. The trench has a floor and sidewalls including a layer of dielectric material, and includes a conductive gate material filled to a selected level and an insulating layer of dielectric material covering the gate material and substantially filling the trench. The top surface of the layer covering the dielectric material in the trench is thus substantially coplanar with the top surface of the top layer. An improved method of forming a MOS-gate device provides a device in which the gate trench is filled with a conductive gate material at a selected level and an insulating dielectric layer is formed whose top surface is substantially coplanar with the top surface of the top layer of the device. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20160056636-A |
| priorityDate | 1999-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.