| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-108 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-48 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-48 |
| filingDate |
1999-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1af6b994b4140195eb45ac21e4f8fb8c |
| publicationDate |
2000-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-20000005666-A |
| titleOfInvention |
Synchronous semiconductor memory device having improved operational frequency margin at data input/output |
| abstract |
A synchronous semiconductor memory device includes a plurality of output latches for temporarily holding data output to the outside in an input / output circuit portion, and a plurality of input latches for temporarily holding data input from the outside. Each latch operates based on an internal clock when exchanging data with an internal memory block, and operates as an in-phase clock when exchanging data with an external clock. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20170013489-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9368168-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9715936-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9281072-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101529291-B1 |
| priorityDate |
1998-06-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |