http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20000001366-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_526cb931f1382d6e016ee651d55e1365 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-03 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76889 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-311 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 1998-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81cf69cd3cc8d994be3b79530aab9b52 |
| publicationDate | 2000-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-20000001366-A |
| titleOfInvention | Method for forming silicide layer of logic circuit portion of composite semiconductor device |
| abstract | The present invention relates to a silicide forming method of a logic circuit portion of a composite semiconductor device, and in particular, the method of the present invention forms a gate conductive layer and a source / drain region of a memory cell array and a gate conductive layer and a source / drain region of a logic circuit. Forming an etch stop barrier layer on the entire surface of the substrate on which the gate conductive layers and the source / drain regions are formed, and forming a bit line and a capacitor contacting the source / drain region of the memory cell through the contact hole of the interlayer insulating layer formed on the barrier layer. In this case, the interlayer insulating film and the barrier film of the logic circuit part are sequentially etched to open the logic circuit part by photolithography and etching processes on the substrate on which the bit line and the capacitor are formed, and then the silicide process is performed on the logic circuit part. Therefore, the present invention can speed up the transistor driving characteristics of a logic circuit without degrading the current characteristics of the memory cell by selectively forming the silicide layer only after the capacitor of the memory cell is formed. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100446860-B1 |
| priorityDate | 1998-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.